Linxiao Wu

Systolic Array-Based CNN Accelerator for Gesture Recognition

Designed a fully hardware INT8 CNN ASIC for 64x64 grayscale gesture recognition, using a fixed network architecture and a 64-PE systolic array in TSMC 65 nm; the chip taped out in July 2026.

• Built a 64-PE INT8 systolic array with approximately 464K MACs per inference and 8 KB of on-chip SRAM.
• Completed RTL implementation, DFT scan-chain design, Cadence Genus synthesis, Innovus place and route, and post-layout verification.
• Developed and quantized CNN models in Python and MATLAB to balance accuracy, silicon area, and hardware cost.

The chip taped out in July 2026. The public repository contains the CNN training and quantization flow; the RTL implementation is not public.

P6-Based Out-of-Order RISC-V Processor

Designed a P6-based RISC-V processor with two-wide fetch, dispatch, and retirement, single-issue out-of-order execution, and in-order commit.

• Implemented a 16-entry ROB, 8-entry reservation station, register map table, and CDB for ROB-tag-based register renaming and out-of-order issue.
• Developed a gshare predictor with a 5-bit GHR and 32-entry BHT/BTB, including two-wide speculative updates and ROB-snapshot recovery.
• Implemented separate load/store queues and a two-way non-blocking data cache with store-to-load forwarding.
• Integrated four-entry MSHR capacity and a four-entry victim cache.

Implemented as a completed computer-architecture project from March through June 2026.

64-Tap 16-Bit FIR Digital Filter Core

Designed a fixed-point FIR core with a multiply-accumulate datapath, CMEM/IMEM, FSM-based controller, and a dual-clock FIFO for clock-domain crossing. Completed RTL, synthesis, STA, and post-synthesis verification.

• Built a complete digital signal-processing pipeline around a parameterized FIR core.
• Integrated dual-clock FIFO logic to handle CDC between low-speed input and high-speed compute domains.
• Validated the design through synthesis and timing analysis using industry-standard EDA tools.

Formal Verification of an N-Body Hardware Accelerator

Used SystemVerilog Assertions in Cadence JasperGold to formally verify the FSM, shift-register pipeline, and address-pointer logic of an N-Body hardware accelerator, exposing design flaws missed by simulation.

• Wrote assertion, assumption, and cover properties for model checking rather than relying on finite testbench-based simulation.
• Found and debugged corner-case bugs including illegal FSM state transitions and a pointer off-by-one overflow issue.
• Improved formal runtime and memory efficiency through IP black-boxing and parameterized pipeline-latency modeling.

8-Bit Microcontroller Core Design

Completed transistor-level design of an accumulator-based 8-bit microcontroller in TSMC 65 nm using a custom 6-bit ISA, including schematic, layout, verification, and post-layout analysis.

• Implemented key modules including PLA control logic, accumulator, adder, shifter, memory latch, bus driver, and 8-byte SRAM.
• Achieved DRC/LVS-clean layout and verified ADD, SHIFT, and full-processor behavior in both pre-layout and post-layout simulation.
• Completed post-layout analysis with a 354 ps critical path and a core area of about 7267.49 um2.

High-Precision SAR ADC Design and Digital Calibration

Joined Associate Professor Xing Xinpeng's research group in senior year to design and verify a capacitor-mismatch digital calibration scheme for a 0.18 um 16-bit SAR ADC.

• Built a MATLAB behavioral model including capacitor mismatch, comparator noise, and other non-idealities to compare foreground calibration and dither-injection LMS calibration.
• Implemented and tested the calibration module on FPGA to evaluate both calibration effectiveness and hardware overhead.
• Improved ENOB from 9.97 bits to 15.67 bits under 3 percent CDAC mismatch.

8-Bit 10 GSPS Time-Interleaved SAR ADC

Participated in the National College IC Innovation and Entrepreneurship Competition and designed an 8-bit 10 GSPS time-interleaved SAR ADC in TSMC 40 nm.

• Completed literature review and architecture analysis, then selected a 16-channel TI-SAR solution with 625 MHz sampling rate per channel.
• Designed and optimized the single-channel SAR ADC in Cadence Virtuoso, including low-power DAC switching, high-linearity sampling switch, low-noise dynamic comparator, and adaptive asynchronous SAR logic.
• Integrated the 16-channel time-interleaved architecture and completed pre-layout verification across input frequencies, process corners, and temperatures.

FPGA-Based Portable Electronic Test System

Built a portable electronic test system integrating a signal generator and oscilloscope on FPGA, and received a university-level excellence award.

• Developed the signal-generator module using DDS to generate adjustable waveform signals.
• Integrated oscilloscope functionality with FFT-based spectrum analysis for signal observation and characterization.
• Took primary responsibility for the signal-generator module and final system integration.